Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition, overlay and other parameters of nanoscale structures.
Overlay error refers to the relative position of structures on different layers of a wafer. The greater the overlay error, the more the structures are misaligned. If the overlay error is too great, the performance of the manufactured electronic device may be compromised.
Overlay error is typically evaluated based on measurements of specialized target structures formed at various locations on the wafer by a lithography tool. The target structures may take many forms, such as a box in box structure. In this form, a box is created on one layer of the wafer and a second, smaller box is created on another layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available.
Image based overlay error measurement typically involves the analysis of images of the specialized target structures to estimate overlay error. Typically, the image analysis involves the recognition of specific target features (e.g., line segments, boxes, etc.) in the image and overlay error is calculated based on relative locations of these features. Typically, the specialized target structures are specific to the image processing algorithm. For example, the line segments associated with the overlay target (e.g., box-in-box target, frame-in-frame target, advanced imaging metrology (AIM) target) are specifically designed to comply with the specifics of the algorithm. For this reason, traditional image based overlay metrology analysis algorithms cannot perform reliably with arbitrary overlay targets or device structures.
In addition, some information is lost because the algorithms work only on specific areas of the image. In other words, the selection of particular line edges, etc. as the focal point for evaluating overlay error ignores contributions that might be made by other pixels in the image.
Moreover, traditional image based algorithms are sensitive to process variations, asymmetry, and optical system errors as these algorithms lack a systematic way to capture the impact of these error sources on the captured images.
Future overlay metrology applications present challenges for metrology due to increasingly small resolution requirements and the increasingly high value of wafer area. Thus, methods and systems for improved overlay measurements are desired.